摘要
在交迭测试体系［１，２］ 的基础上提出了一种利用二选一开关辅助扫描寄存器的排序、能够实现最小测试应用时间的单扫描链的构造方法，给出了单扫描链的构造规则．此外还分析了由于二选一开关的引入带来的硬件开销问题，提出了一个能够减少硬件开销的算法．
The paper proposes a method to construct single scan chain that is based on the overlapped test scheme, assisted by the 2 to 1 multiplexers and can realize the minimum test application time. The constructing rules are given. The paper also analyses the hardware overhead due to the introduction of the multiplexers and proposes an algorithm that can reduce the hardware overheads.
出处
《计算机学报》
EI
CSCD
北大核心
1999年第12期1280-1288,共9页
Chinese Journal of Computers
关键词
集成电路
测试
最小测试
应用时间
单扫描链
IC test, minimum test application time, single scan chain, hardware overhead.
