基于FPGA的SpaceWire路由器设计

Design of SpaceWire router based on FPGA

针对SpaceWire的应用需求,在对SpaceWire标准协议及其路由机制介绍的基础上,设计并实现了1种SpaceWire路由器。路由器以FPGA为核心,带有8个SpaceWire链路接口、2个USB总线接口以及1个Time_Code接口,采用Verilog HDL硬件描述语言设计开发SpaceWire路由器IP核。经过对SpaceWire路由器数据传输的可靠性和实时性测试,结果表明SpaceWire路由器通信速率可达200 Mb/s,数据传输具有较高的可靠性和实时性。

To fulfill the needs for the application of SpaceWire,a design is provided to achieve a SpaceWire router based on the introduction of SpaceWire standard and routing mechanism.The SpaceWire Router that contains eight SpaceWire link interfaces,two USB interfaces and one Time_Code interface adopts FPGA as control unit,the logic design of the SpaceWire router IP is developed with the Verilog HDL.The reliability and real-time of data transmission are tested,the test results show that the SpaceWire router has high reliable and real-time performance.