应用于UWB的128点FFT处理器的物理设计

Physical design of 128-point FFT processor applied in UWB system

在SoC Encounter 5.2的平台上,对应用于UWB无线通信的128点FFT处理器进行了物理设计.在前端综合以及可测性设计后导出的FFT处理器门级网表的基础上,采用SMIC 0.18μm CMOS工艺,进行了布图规划、电源规划、布局、时钟树综合、静态时序分析与优化、布线等步骤.在完成详细布线之后,对该设计进行物理验证,包括设计规则检查(DRC)和版图与原理图一致性检查(LVS),并使用Formality成功通过了逻辑等效验证.该FFT芯片时钟频率为76.9 MHz,芯片面积约为6.5 mm2.

After logic synthesis and DFT design, the physical design of 128 -point FI;T processor ap- plied in UWB system is introduced. Based on SMIC 0.18 μm CMOS technology, the back - end de- sign flow includes floorplan, powerplan, placement, clock tree synthesis, static timing analysis and optimization using SoC Encounter 5.2. After nano route, the physical verification including DRC （design rule check） and LVS （layout versus schematic） and formality are carried on. The clock frequency of this FIT chip is 76.9 MHz, and the chip area is about 6.5 mm^2.