期刊文献+

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET
原文传递
导出
摘要 A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance. A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第7期14-19,共6页 半导体学报(英文版)
关键词 gate tunneling current analytical model spacer dielectrics DIBL subthreshold slope gate tunneling current analytical model spacer dielectrics DIBL subthreshold slope
  • 相关文献

参考文献20

  • 1Choi C H, Nam K Y, Yu Z, et al. Impact of gate direct tunneling current on circuit performance: a simulation study. IEEE Trans Electron Devices, 2001, 48:2823.
  • 2Intemational Technology Roadmap for Semiconductors. http:// public.itrs.net/Files/20011TRS/Home.html.
  • 3Taur Y. CMOS design near the limits of scaling. IBM Journal of Research & Development, 2002, 46(2/3): 213.
  • 4Sirisantana N, Wei L, Roy K. High performance low-power CMOS circuits using multiple channel length and multiple ox- ide thickness. Proc IEEE ICCD, 2000:227.
  • 5Hamzaoglu F, Stan M. Circuit level techniques to control gate leakage for sub 100 nm CMOS. Proc ISLPED, 2002:60.
  • 6Roy K, Mukhopadhyay S, Meimand H M. Leakage current mech- anisms and leakage reduction techniques in deep-sub micrometer CMOS circuits. Proc IEEE, 2003, 91(2): 305.
  • 7Lee D, Blaauw D, Sylvester D. Analysis and minimization tech- niques for total leakage considering gate oxide leakage. Proe ACM/IEEE DAC, 2003:175.
  • 8Lee D, Blaauw D, Sylvester D. Gate oxide leakage current ana- lysis and reduction for VLSI circuits. IEEE Trans VLSI Syst, 2004, 12(2): 155.
  • 9Sultania A K, Sylvester D, Sapatnekar S S. Trade-offs between gate oxide leakage and delay for dual Tox circuits. Proceedings of Design Automation Conference, 2004:761.
  • 10Sirisantana N, Roy K. Low-power design using multiple channel lengths and oxide thicknesses. IEEE Design & Test of Comput- ers, 2004, 21(1): 56.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部