摘要
An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors.An adder determines the overall performance of the circuits in most of those systems.In this paper we propose a novel 1-bit full adder cell which uses only eight transistors.In this design,three multiplexers and one inverter are applied tominimize the transistor count and reduce power consumption.The power dissipation,propagation delay,and power-delay produced using the new design are analyzed and com-pared with those of other designs using HSPICE simulations.The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value.The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.
An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration （VLSI） systems such as application-specific digital signal processing （DSP） and microprocessors.An adder determines the overall performance of the circuits in most of those systems.In this paper we propose a novel 1-bit full adder cell which uses only eight transistors.In this design,three multiplexers and one inverter are applied tominimize the transistor count and reduce power consumption.The power dissipation,propagation delay,and power-delay produced using the new design are analyzed and com-pared with those of other designs using HSPICE simulations.The results show that the proposed adder has both lower power consumption and a lower power-delay product （PDP） value.The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.
基金
Project (No.61071062) supported by the National Natural Science Foundation of China
