FPGA上SHA-1算法的流水线结构实现

Implementation of Pipeline Structure on FPGA for SHA-1

哈希算法SHA-1算法广泛地应用于电子商务、商用加密软件等信息安全领域。通过对SHA-1算法的深入分析,提出了流水线结构的硬件实现方案。通过缩短关键路径,使用片内RAM代替LE寄存器实现流水线中间变量的数据传递,有效地提高了工作频率和单位SHA-1算法的计算速度。这种硬件结构在Altera系列芯片上的实现性能是Altera商用SHA-1算法IP核的3倍以上。

Hash algorithm SHA-1 is used widely in cryptographic applications such as E-commerce and commercial encryption softwares.By making an overall analysis,implementation of pipeline structure was proposed.By shorting the critical path,using inside RAMs to realize the data translation instead of LE,we improved the frequency and the speed of per SHA-1 unit.The performance on FPGAs of Altera is three times faster of commercial IP cores for SHA-1.