期刊文献+

快速单精度浮点运算器的设计与实现 被引量:4

Design and implementation of fast single-precision floating-point arithmetic unit
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摘要 浮点运算单元FPU(Floating-point Unit)在当前CPU的运算中地位越来越重要,论文中实现了一种基于FPGA的快速单精度浮点运算器.该运算器采用了流水线和并行计算技术,使得浮点数运算的速度有了显著的提高.在QUARTUSII 7.1系统上对运算器已仿真成功,结果表明它可以运行在40.5MHz时钟工作频率下,能快速准确地完成各种加、减、乘和除算术运算. It is the trend to adopt the Floating-point Unit(FPU)in the structure of CPU.A fast single precision floating point arithmetic unit is proposed and realized based on the FPGA.Pipelining and parallel processing are applied to the arithmetic unit,so that floating point operation speed has been significantly improved.The successful simulation results on QUARTUSII 7.1 show that the arithmetic unit can operate at 40.5 MHz clock frequency and complete all kinds of addition,subtraction,multiplication and division operations quickly and accurately.
出处 《河北工业大学学报》 CAS 北大核心 2011年第3期74-78,共5页 Journal of Hebei University of Technology
基金 河北省自然科学基金(F2007000096)
关键词 FPGA(现场可编程逻辑门阵列) 单精度 并行处理 并行加法器 阵列乘法器 阵列除法器 FPGA(field-programmable gate array) single-precision parallel processing parallel adder array multiplier array divider
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参考文献7

  • 1黄志军,张鹏,童家榕.FPGA/CPLD结构分析[J].微电子学,1998,28(5):345-353. 被引量:9
  • 2周宁宁,陈燕例,李爱群.基于FPGA技术的浮点运算器的设计与实现[J].计算机工程与设计,2005,26(6):1578-1581. 被引量:11
  • 3MayPhyoThwal. Implementation of adder-subtracter design with Verilog HDL world academy of seience [J]. Engineering and Technology, 2008, 39: 123-127.
  • 4王晓莉,黄伟,王典洪.高速流水线浮点加法器的FPGA实现[J].电子元器件应用,2009,11(4):62-65. 被引量:3
  • 5NhonTQuach, NaofumiTakagi, MichaelJFlynn. SystematiclEEEroundingmethodforhigh-speedfloating-pointmultipliers [J]. IEEETransactions on Very Large Scale Integration (VLSI) Systems, 2004, 12 (5): 511-521.
  • 6Chinnaiyan Senthipari. Low Energy, low latency and high speed array divider circuit using a shannon theorem based adder cell [J]. Recent Ptenson Nanotechnology, 2009, 3 (1): 61-72.
  • 7WAYNE L. Pipelining and transposing heterogeneous array designs [J]. Journal of VLSI Signal Processing, 1993, 5 (1) : 7-20.

二级参考文献8

共引文献20

同被引文献27

  • 1刘德建,郑继禹.基于流水线技术的FIR滤波器的设计与实现[J].电测与仪表,2008,45(6):54-56. 被引量:2
  • 2Wei-WuHu Fu-XinZhang Zu-SongLi.Microarchitecture of the Godson-2 Processor[J].Journal of Computer Science & Technology,2005,20(2):243-249. 被引量:52
  • 3徐东明.实现快速乘法的几种改进贝斯算法[J].西安邮电学院学报,2006,11(1):61-65. 被引量:3
  • 4朱蕾,王斌.基于FPGA的浮点FIR滤波器的设计与实现[J].微电子学与计算机,2007,24(7):59-62. 被引量:1
  • 5ANSI/IEEE Std 754-2008: Binary Floating-Point A-rithmetic[S]. IEEE SA Standards Board,2008:6-28.
  • 6胡伟武,陈云霁,肖俊华,等.计算机体系结构[M].北京:清华大学出版社,2011:163-178.
  • 7Steve Kilts.高级FPGA设计一结构、实现和优化[M].孟宪元,译.北京:机械工业出版社,2009:96-104.
  • 8Erie MA,Hickmann BJ, Schulte MJ. Decimal float-ing-point multiplication [J ]. IEEE Transactions onComputers, 2009,58(7): 902-916.
  • 9Jain S,Erraguntla V,Vangal SR. A 90mw/gflop3. 4ghz reconfigurable fused/continuous multiply-accu-mulator for floating-point and integer operands in65nm [C]// 2010 IEEE 23rd International Conferenceon VLSI Design, 2010:252-257.
  • 10IEEE Standard for Binary Floating-Point Arithmetic:New York, NY IO017,USA. 1985.

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