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Enhanced Offset Averaging Technique for Flash ADC Design 被引量：2

Enhanced Offset Averaging Technique for Flash ADC Design
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摘要 This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology. This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
作者 Siqiang FAN He TANG Hui ZHAO Xin WANG Albert WANG Bin ZHAO Gary G ZHANG
机构地区 Freescale Semiconductor Department of Electrical Engineering Skyworks Solutions
出处 《Tsinghua Science and Technology》 SCIE EI CAS 2011年第3期285-289,共5页 清华大学学报（自然科学版（英文版）
关键词 analog-to-digital converter flash analog-to-digital converters （ADC） integrated circuit （IC） offset averaging resistor averaging capacitor averaging analog-to-digital converter flash analog-to-digital converters （ADC） integrated circuit （IC） offset averaging resistor averaging capacitor averaging
分类号 TN912.3 [电子电信—通信与信息系统] TN792 [电子电信—电路与系统]
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参考文献7

  • 1Kattmann K, Barrow J. A technique for reducing differen- tial nonlinearity errors in flash A/D converters. In: Proc. IEEE International Solid-State Circuits Con., San Fran- cisco, CA, USA, 1997: 170-171.
  • 2Wang Z-Y, Pan H, Chang C-M, et al. A 600 MSPS 8-bit folding ADC in 0.18pxn CMOS. In: Tech. Digest, IEEE Symp. VLSI Circuits, 2004: 424-427.
  • 3Mulder J, Ward C M, Lin C-H, et al. A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-pro CMOS. IEEE Journal of Solid State Circuits, 2004, 39(12): 2116-2125.
  • 4Scholtens P C S, Vertregt M. A 6-b 1.6-Gsample/s flash ADC in 0.18-jxna CMOS using averaging termination. IEEE Journal of Solid-State Circuits, 2002, 37(12): 1599- 1609.
  • 5Sandner C, Clara M, Santner A, et al. A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-~tm digital CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(7): 1499-1505.
  • 6Jiang X, Chang F. A1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. IEEE Journal of Solid State Circuits, 2005, 40(2): 532-535.
  • 7Pan H. A 3.3-V 12-b 50-MS/s A/D converter in 0.6-~m CMOS with 80-dB SFDR [Dissertation]. University of California, Los Angeles, USA, 1999.

同被引文献12

引证文献2

Tsinghua Science and Technology
2011年 第3期

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