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Metric多核子方法划分编译算法设计与实现

Design and implementation of slice partition compilation algorithm for Metric multi-core
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摘要 为解决编程模型严重阻碍多核处理器性能的进一步提升,尝试将编程单位即方法(procedure)引入到多核处理器结构设计中,提出了面向高性能计算的Metric(Method Centric)以方法为中心多核架构且采用编译技术,将函数划分成大小相当的子方法(slice),以支持处理器微结构设计.实验表明:子方法划分算法的突破,将为Metric多核完整编译工具链的建立和模拟器的编写奠定基础. Programming model has become one of the handicaps in multi-core era.To counter to this bottleneck,a novel multi-core architecture,namely Metric(Method centric),is proposed in this paper,which attempts to bring the concept of procedure in programming model into computer architecture design.Basing on Metric multi-core,a slice partitioning compilation pass which tries to divide procedures into finer grains of similar size,namely slice,is investigated in details.Preliminary experiment results validate its effectiveness,and the algorithm is of great importance to Metric compiler tool chain and simulator setup.
出处 《哈尔滨工业大学学报》 EI CAS CSCD 北大核心 2011年第7期76-79,共4页 Journal of Harbin Institute of Technology
基金 国家自然科学基金资助项目(90818016) 中国博士后科学基金资助项目(20070420868) 黑龙江省自然科学基金资助项目(F200822)
关键词 多核 编程模型 编译技术 multi-core programming model compilation
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  • 1WAINGOLD E, TAYLOR M, SARKAR V, et al. Ba- ting it all to software: RAW machines[J]. IEEE Com- puter, 1997, 30(9):86-93.
  • 2MAI K, PAASKE T, JAYASENA N, et al. Smart mem- ories : A modular reconfigurable architecture [ C ]//Pro- ceedings of the 27th Annual International Symposium on Computer Architecture. New York, NY: ACM, 2000: 161 -171.
  • 3University of TEXAS at Austin. Fera-op Reliable Intelli- gently adaptive processing system [ EB/OL ]. [2010 -04 - 19]. www. cs. utexas, edu/-TRIPS/.
  • 4University of Washingon. WaveScalar [ EB/OL ]. [ 2010-04-19 ]. http ://wavescalar. cs. washington, edu.
  • 5SANKARALINGAM K, NAGARAJAN R, McDONAID R, et al. Distributed microarchitectural protocols in the trips prototype processor [ C ]//Proceedings of the 39th Annual IEEE/ACM International Symposium on Micro- architecture. Washington, DC : IEEE, 2006 : 480 - 491.
  • 6SWANSON S, PUTNAM A, MERCALDI M, et al. Are- a-performance trade-offs in tiled dataflow architectures [C]//Proceedings of the 33rd Annual International Symposium on Computer Architecture. Washington, DC: IEEE, 2006:314-326.
  • 7University of Amsterdam. MuhiProcessor System-on- Chip (MP-SoC) Design[EB/OL]. [2010 -04-19]. http ://www. science, uva. nl/research/csa/.
  • 8BELL I, HASAASNEH N, JESSHOPE C. Supporting microthread scheduling and synchronisation in CMPs [J]. Intl J Parallel Processing, 2006, 34(4) : 1 -9.

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