基于FPGA的阵列乘法器的设计与实现

Based on the array FPGA on time-multiplier of design and implementation

先对乘法器进行了分析,然后用现场可编程门阵列(F P G A)实现了阵列乘法器,并分析了设计原理。

This paper analyzed the operation of multiplier unit first,then realized array multiplier with FPGA,and described the design principle.