摘要
介绍了匹配滤波器原理,分析了匹配滤波并行处理的算法,提出了一种适合高速处理的并行数字匹配滤波器的设计方法。使用Matlab软件进行了仿真,根据仿真结果证明了此设计方法可行。给出了利用可编程门阵列(Field-Programmable Gate Array,FPGA)实现16阶高速并行数字匹配滤波器的方案,指出了实现的要点。在系统中进行了性能测试,结果表明,采用该并行处理算法实现的数字匹配滤波器适合高速信号处理。
The principle of matched filter is introduced in this paper first.The algorithm of parallel matched filter is analyzed and the design method of parallel digital matched filter is presented.The parallel digital matched filter is simulated with Matlab,and the simulation result shows the designed filter is feasible.A sixteen-order high-speed parallel digital FIR filter based on the FPGA is implemented by using this new algorithm and the main point is analyzed.Finally,the performance test is implemented in this system,and the result indicates that the digital matched filter by adopting the parallel processing algorithm is suitable to high-speed signal processing.
出处
《无线电工程》
2011年第7期62-64,共3页
Radio Engineering
