基于预测缓存的低功耗TLB快速访问机制

Fast and low power TLB access mechanism with prediction buffer

基于存储器访问局部性原理,提出了一种基于预测缓存的低功耗转换旁置缓冲器(TLB)快速访问机制。该机制采用单端口静态随机存储器(SRAM)代替传统的内容寻址存储器(CAM)结构,通过匹配搜索实现全相连TLB的快速访问,在两级TLB之间设计可配置的访问预测缓存,用于动态预测第二级TLB访问顺序,减少第二级TLB搜索匹配的延时,并有效降低第二级TLB访问功耗。采用该机制明显降低了TLB的缺失代价,当第一级TLB缺失时访问第二级TLB的平均访问延时接近1个时钟周期,约为原有平均访问延时的20%,增加的面积开销仅为原内存管理单元的1.81%左右,具有低成本、低功耗的特征。

This paper proposed a fast and low power TLB access mechanism with prediction buffer based on memory access locality principle,and designed a two-level TLB structure implemented by SARM instead of CAM to achieve fast access of the full associated TLB.Between the two levels of the introduced TLB,an independent and hardware configurable prediction buffer was designed to dynamically predict the access sequences of the second level TLB,which could reduce its access penalty when the first level TLB missed and significantly reduce the dynamic power consumption with little control logic.Experiment shows that compared with the traditional two-level TLB structure,the average access cycles of the second level TLB are about 20% of the traditional one,with only 1.81% area increment,which support low power and low cost embedded application.