纳米CMOS电路逻辑等效变换

Logic Equivalent Transformation for Nano-meter CMOS Hybrid Circuits

针对纳米CMOS电路连通域结构约束,该文提出了基于逻辑复制方法的电路等效变换技术以降低电路映射复杂性。首先通过对电路中所有的门扇出值进行排序来选定基准高扇出值;然后对于高扇出门单元通过二次方程式计算变换前后复杂度,对复杂度降低的高扇出门单元执行逻辑复制并进行扇出分割。与传统插入反相器方法网表转换法比较,结果表明使用该文提出的方法电路不仅更快速地被映射到纳米混合电路单元上,而且具有更好的时延特性。

Regarding the connectivity domain constraint in nano-meter circuit architecture,this paper proposes a circuit equivalent transformation method based on logic replication for reducing mapping complexity.The fanout degrees of all gates in a circuit are recorded and sorted to select the reference of high fanout value.Then a quadratic equation is formulated to evaluate whether the mapping complexities of the gates are reduced.Finally,the gate which has fanout degree larger than the reference high fanout value will be replicated if the complexity degree is reduced.The proposed method can not only make circuits easily to map,but also achieve better timing than buffer insertion.