基于FPGA的UART设计与实现

Design and implementation of UART based on FPGA

为在CPCI总线数字I/O模块上实现UART(universal asynchronous receiver transmitter,通用异步接收发送器)接收功能,提出了一种基于现场可编程门阵列器件(FPGA)的UART设计与实现方案。在Altera Quartus Ⅱ开发平台上采用Verilog HDL语言和其自带的IP CORE实现UART的接收。最后借助于QuartusⅡ集成开发环境中提供的SignalTapⅡ嵌入式逻辑分析仪进行验证,结果表明,该UART工作稳定可靠。

In order to realize the UART（universal asynchronous receiver transmitter）receive function in the CPCI bus digital I/O modules,we proposed a design and implementation scheme based on the field programmable gates array（FPGA）.In the Altera Quartus II development platform we using Verilog HDL language and its own IP CORE to realize the receive function.Finally we use SignalTapⅡembedded logic analyzers which is provided by Quartus Ⅱ integrated development environment to verify,the results show that the UART modeule is stable and reliable.