功率VDMOS器件ESD防护结构设计研究

Study of ESD Protection Structure for Power VDMOS Devices

随着半导体工艺的不断发展,器件的特征尺寸在不断缩小,栅氧化层也越来越薄,使得器件受到静电放电破坏的概率大大增加。为此,设计了一种用于保护功率器件栅氧化层的多晶硅背靠背齐纳二极管ESD防护结构。多晶硅背靠背齐纳二极管通过在栅氧化层上的多晶硅中不同区域进行不同掺杂实现。该结构与现有功率VDMOS制造工艺完全兼容,具有很强的鲁棒性。由于多晶硅与体硅分开,消除了衬底耦合噪声和寄生效应等,从而有效减小了漏电流。经流片测试验证,该ESD防护结构的HBM防护级别达8 kV以上。

With the development of semiconductor technology,the gate oxide becomes more and more thin as the feature size gets to shrink,to make the chance of electrostatic discharge damage to device increases greatly.The ESD protection structure of a polysilicon back to back zener diode was designed for the power VDMOS devices.The polysilicon back to back zener diode was made through different doping in different regions of polysilicon on the gate oxide.This structure was compatible with the existing power VDMOS manufacturing process completely,and its robustness was excellent.The substrate coupling noise,parasitic effects and so on are eliminated by separating the polysilicon from bulk silicon,which reduced the leakage current effectively.The test results after tape out show that the HBM protection level of this ESD protection structure is more than 8 kV.