高共模输入电平的迟滞比较器设计

Design of Hysteresis Comparator with High Common Mode Input Level

提出了一种新颖的基于双极工艺的迟滞比较器,该电路在保持了传统电路的高共模输入电平和低功耗的优点的同时,在电路结构上比传统的电路节省了一级射随器。此外,为了保证该迟滞比较器中两级运算放大器的稳定性还进行了频率补偿的研究,并对该电路的稳定性进行了仿真,其仿真结果保证了60°的相位裕度。该迟滞比较器的电路使用华润上华1μm双极晶体管工艺实现,芯片测试结果表明,其上阈值点为7.4 V,下阈值点为6.92 V,迟滞电压约为0.48 V,输出高电平约为0.76 V,电路工作稳定。

A novel hysteresis comparator based on the bipolar technology was proposed.This comparator has the advantages of high common mode level and low power dissipation that the traditional circuit structure possesses.In comparison to the traditional circuit,an emitter follower is reduced.In addition,in order to remain the stability of the two-stage operational amplifier in this hysteresis comparator,the frequency compensation was studied.The circuit stability was simulated,and the phase margin attained 60°.This hysteresis comparator was realized by CSMC 1 μm bipolar technology.The measured results show that the upper threshold voltage is 7.4 V,the lower threshold voltage 6.92 V,the hysteresis voltage is 0.48 V,the output high level is about 0.76 V,and the circuit works stably.