基于FPGA的Viterbi算法改进及其实现

FPGA-based Improvement and Implementation of Viterbi Algorithm

为了在不改变译码效果的条件下,达到提高译码器的译码速度的目的,对传统的Viterbi算法的实现方法提出了两点改进:简化分支度量计算和复用加比选单元分组。FPGA实现以后显示,在获得同等译码性能的条件下,新的实现结构比改进前仅仅多耗费了可以忽略的资源,却可以达到接近原结构3倍的吞吐量和接近2倍的最大系统工作频率。

For the purpose of improving decoding speed of decoder without influence on decoding effect,two improvements（simplifing branch metric computation and grouping of reusing addition,comparison,selection units） for implementation of the traditional Viterbi algorithm are presented.FPGA implementation appears that the new architecture with same decoding performance as old one but negligible extra resource consumption can get almost three times of throughput and two times of system maximum working frequence in comparison with the architecture before modification.