LPDDR2在LTE终端的PCB叠层结构设计

Design of PCB Layout's Stackup Structure with LPDDR2 for LTE Terminals

研究了长期演进(LTE)终端的印刷电路板(PCB)叠层设计过程及工程上常用的材料规格,并讨论了叠层结构对阻抗、信号回路的影响。分析了在设计带有低功耗双倍数据速率(LPDDR2)芯片的LTE终端电路板时如何根据阻抗的需要设计叠层结构,并结合实际工艺制作的情况,重点提出在设计叠层结构时应注意参数改变问题,分析了参数改变的原因及解决方法。

This paper discusses the design of the long term evolution （LTE） terminals stackup structure of PCB as well as the material specifications used in engineering design. It also studies the affect of the stackup structure on the impedance and routing rules. The design of the stackup structure according to the needs of impedance is analyzed when we are drawing a LTE terminals PCB with LPDDR2 chips. Combined with the actual fabrication, this paper highlights that we should pay attention to the changing of the parameters in the design of stackup structures. The causes to parameter changes and the solutions of the problem are also analyzed.