MFSM结构铁电薄膜系统I-V特性研究

A Study on the I-V Characteristics of Ferroelectric Thin Film Systems with Structure of MFSM

为制备符合铁电场效应晶体管（ＦＦＥＴ）及铁电存储二极管（ＦＭＤ）要求的高质量铁电薄膜，采用激光脉冲沉积方法（ＰＬＤ）制备了Ａｕ／ＰＺＴ／ｐ－Ｓｉ／Ａｕ 和Ａｕ／ＰＺＴ／ＢＩＴ／ｐ－Ｓｉ／Ａｕ 多层结构的两种铁电薄膜系统。分析表明，在不同的电压范围，起主导作用的导电机制不同：电压低于１Ｖ时，漏电流遵循欧姆定律，电压在２．２～３．０Ｖ时，空间电荷限制电流（ＳＣＬＣ）占主导地位。Ｉ－Ｖ 特性曲线的结果表明Ａｕ／ＰＺＴ／ＢＩＴ／ｐ－Ｓｉ／Ａｕ 结构比Ａｕ／ＰＺＴ／ｐ－Ｓｉ／Ａｕ 结构的漏电流密度低两个数量级，Ｉ－Ｖ 特性曲线回滞窗口增大０．３Ｖ，这说明ＰＺＴ铁电薄膜与Ｓｉ衬底之间加入ＢＩＴ铁电层有助于降低漏电流密度。

The ferroelectric thin film systems with multilayer structure of Au/PZT/p Si/Au and Au/PZT/BIT/p Si/Au were fabricated by pulsed laser deposition (PLD) technique.Electrical properties of the Metal/Ferroelectric/Semiconductor/Metal(MFSM)structures have been characterized through the measurements of bias voltage dependence of current and the conductivity behavior has been discussed.The results show that the main conductive mechanism is different at different voltage areas:the leakage current follows the Ohm Law when the voltage is lower than 1V,and the Space Charge Limited Current(SCLC)is primary when the vlotage is 2.2 ~ 3.0 V.The I V curve of the Au/PZT/BIT/p Si structure show that the leakage current density is two orders lower and memory window is 0.3V larger than those of the Au/PZT/p Si structure.This results suggest that the growth of the BIT buffer layer redound to decrease the leakage current density and enlarge the memory window.