并联交错数字APFC的研究

Research on Paralleled Interleaved Digital APFC

有源功率因数校正器(APFC)的应用场合日益增多,采用两级或多级并联交错APFC可以有效地降低电流纹波,减小电感尺寸,更好地应用于大功率场合。文中在首先描述两级交错并联APFC电路结构和工作原理的基础上,提出了两级均流的控制方法及其数字实现的基本方法。设计了基于dsPICDSC的数字实现方案,采用Matlab/Simulink对整个APFC系统进行仿真分析后,对该方案进行了实验验证。结果表明数字实现并联交错APFC是可行的,并且具有很好的纹波抑制效果和均流特性。

Active power factor correction（APFC） is used in an increasing number of applications.Two-stage or multi-stage interleaved APFC which can effectively reduce the current ripple and inductor size,is better used in high power applications.The paper firstly described the circuit structure and working principle of two-stage interleaved APFC,then proposed a control method and its digital implementation for load balance.Design a digital implementation of APFC based on dsPIC DSC,and use Matlab/Simulink to simulate the APFC system.At last an experiment to verify this program is done.The results show that the digital implementation of interleaved APFC with good ripple rejection and load balance characteristics is feasible.