一种适用于相变存储器的低噪声时钟发生器

A Low Noise Clock Generator for Phase Change Memory

基于相变存储器的特性,设计了一种具有低功耗、低噪声的时钟发生器。该时钟由压控振荡器产生,并通过时钟控制电路转换为相变存储器存储操作所需的reset、set信号。由于纳米尺寸下的相变存储器件受噪声影响严重,该电路降低了外围驱动对相变存储单元的低频噪声干扰,能够改进相变存储器性能。电路采用40 nm CMOS工艺设计,电源电压为1.8 V,功耗为1.26 mW,RMS抖动为0.83 ps,p-p抖动为5.14 ps,芯片面积为80μm×90μm。

A low phase noise and low power clock generator for phase change memory（PCM） was designed.In this circuit,clock signal generated from a voltage controlled oscillator（VCO） was transformed into reset and set pulses to operate PCM cells by timing control circuit.Considering that the PCM device in nanoscale is influenced by low-frequency noise,the clock circuit reduced the noise of PCM driving circuit and thereby improved performance of PCM device.Fabricated in 40 nm CMOS process,the device had an RMS jitter of 0.83 ps and a p-p jitter of 5.14 ps,and the chip occupied an area of 80 μm × 90 μm and consumed 1.26 mW of power from a single 1.8 V supply.