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随机掺杂波动引起的6T SRAM访问失效率分析

Analysis of Access-Time Failure Probability Due to Random Dopant Fluctuation in 6T SRAM
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摘要 对6T SRAM的访问时间进行解析,得到在随机掺杂波动影响下6T SRAM访问时间的模型,结果与HSPICE仿真结果相符。通过分析偏置技术与访问失效率的密切关系,提出采用偏置技术降低存储单元访问失效率的方法。 In nano-scaled CMOS circuits,random dopant fluctuations would cause significant variations in threshold voltage（Vth） of transistors,which have great effects on both device and logic circuits.An analytical access-time model for 6T SRAM was developed based on RDF,and the analytical results agreed with HSPICE simulation.By analyzing the relation of access-time failure probability with bias control technology,a bias control technology was proposed to reduce access-time failure probability.
作者 柏娜 吕百涛 杨军 时龙兴
机构地区 东南大学国家专用集成电路系统工程技术研究中心 新加坡国立大学超大规模集成电路与系统设计实验室 安徽大学电子信息工程学院
出处 《微电子学》 CAS CSCD 北大核心 2011年第4期599-602,616,共5页 Microelectronics
基金 国家建设高水平大学公派研究生基金资助项目
关键词 随机掺杂波动 SRAM 访问失效率 偏置控制技术 Random dopant fluctuation SRAM Access failure probability Bias control technology
分类号 TN401 [电子电信—微电子学与固体电子学] TN406 [电子电信—微电子学与固体电子学]
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参考文献11

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微电子学
2011年 第4期

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