基于FPGA的地震计标定信号发生器的设计与实现

Design and implementation of signal generator for seismometer calibration based on FPGA

为配合地震计电磁信息采集系统对地震计进行标定,设计一款基于FPGA的地震计标定信号发生器。以AlteraEP2C8T144C8型FPGA和16位串行DAC芯片DAC8560为核心,利用直接数字频率合成技术、m序列生成技术等产生地震计标定所需信号,设计电路对信号进行偏置、滤波、数字程控调幅、电压电流转换以输出特定的电压、电流信号。使用Verilog HDL语言实现系统软件。将标定信号发生器应用于实验室开发的地震电磁信息采集系统,结果表明,系统可产生地震计标定所需正弦波、方波、伪随机二进制信号,完成地震计标定工作。

In order to calibrate seismometer with electromagnetic data acquisition system,a signal generator based on FPGA for seismometer calibration is presented.Altera EP2C8T144C8 FPGA and a 16-bit serial DAC called DAC8560 are used as the core of the system.DDS and m-sequence are used to generate signal for seismometer calibration.In order to output specific current and voltage signal for seismometer calibration,some circuits such as bias circuit,filter,amplitude modulation circuit,V/I conversion circuit and so on are designed.Based on Verilog HDL language,system software is realized.The signal generator is used in seismic electromagnetic data acquisition system developed by laboratory.The results show that it can generate sine wave,square wave,pseudo-random binary signal for seismometer calibration and complete calibration work.