摘要
针对目前多数的FPGA都支持浮点IP核,却较少关注数据源获取的问题,提出了一种数据格式转换方法。使用VHDL语言,采用流水线处理方式将ASCII码所表示的一定范围内的实数转换为单精度浮点数。经过ModelSim功能仿真和实际下载验证,该设计的转换时间可达10-1μs量级。利用Matlab对转换结果进行分析验证,该方法的转换精度可达10-9。在此采用的设计结构合理,可为浮点IP核提供数据源。
According to the problem that most FPGA support floating-point IP core but have little attention to the acquisition of data source,a range of real number presented by ASCII code is converted to single precision floating-point by pipeline processing with VHDL language.Through functional simulation with Modelsim and download verification,the conversion accuracy can reach 10-9 and the conversion time is 10-1μs magnitude.This design has a rational construction and can provide data source for floating-point IP core.
出处
《现代电子技术》
2011年第16期110-112,共3页
Modern Electronics Technique
基金
国家自然科学基金资助项目(60672139
60972160)
关键词
单精度浮点数
流水线处理
FPGA
IP核
single precision floating-point
pipeline processing
FPGA
IP Core
