共轭梯度求解器的FPGA设计与实现

Design and implementation of conjugate gradient iterative solver on FPGA

针对共轭梯度(CG)迭代算法软件执行效率低、实时性差的缺点,提出一种基于现场可编程逻辑门阵列(FPGA)平台的CG迭代求解器。设计采用软硬件结合的方式构建整个系统,CG协处理器执行CG迭代算法中计算量大、控制简单的代码,以达到硬件加速的目的。控制复杂、计算量较少的代码则依旧在微处理上执行。设计采用行交错数据流,使得整个系统完全无停顿的运行,提高了计算性能。实验结果表明,与软件执行相比,硬件CG协处理器可以获得最高5.7倍的性能加速。

To overcome the disadvantage of inefficient and bad real-time capability in software version Conjugate Gradient （CG） iterative solver, a CG iterative solver was designed and implemented on Field Programmable Gate Array （FPGA） platform. The design of CG iterative solver was based on hardware/software co-design. Hardware CG co-processor implemented the code of enormous computation and simple control, which could accelerate the system. The code of control complexity and less calculation was still performed in the microprocessor. The use of row-interleaved data flow could make the system not to stall to improve performance. The experimental results illustrate that hardware CG iterative solver can speed up about 5.7 times over the software version of the same algorithm.