锁相环小数N分频频率综合器中的Sigma-delta调制器设计

Design of Sigma-delta Modulator in Fractional-N PLL Frequency Synthesizer

介绍了一种应用于小数N分频频率综合器的工作干20MHz的Sigma—delta调制器的设计，采用3个一阶电路级联的MASH1—1—1结构的噪声整形电路。电路设计利用Verilog硬件描述语言进行描述，在modelSimSE6．2b中通过了功能仿真，并在XUPVirtex-IIProFPGA开发板上进行了验证，最终呆用TSMC0．13btmCMOS工艺，完成了电路版图并通过了DRC和LVS验证。芯片面积为180μm×160μm，平均功耗为1．0596～1．0704mW。

The design of the Sigma-delta modulator working on 20 MHz is described in this paper, which is used in the fractional-N frequency synthesizer. The noise shaping circuit of MASHI-1-1 structure cascading of three first-order circuits is used. Verilog hardware description language is used to describe the circuit. The circuit passes the functional simulation in modelSim SE 6.2b and is verified in the XUP Virtex-II Pro FPGA development board. Eventually, the TSMC 0.13 p,m CMOS process is adopted, the circuit layout is finished, and the correct DRC ＆ LVS verification is got. The chip＇s area is 180 μm×160μm, and the average power consumption in this chip is between 1.059 6-1.070 4 mW.