摘要
为了对抗有源干扰,雷达系统要求频率合成器具有频率捷变功能;同时要求其杂散抑制越高越好,特别是在输出信号带宽较宽的情况下更是如此。受体积和成本的限制,目前的捷变频频率合成器广泛采用基于直接数字合成(DDS)技术的变频方法。本文基于低杂散,对采用DDS的捷变频频率合成器技术进行了研究,并介绍一种采用时钟频率高达3.2 GHz的新型DDS集成电路的低杂散捷变频频率合成器的设计与实现方法,设计得到的捷变频频率合成器带宽为250 MHz,其杂散抑制指标可满足全频段优于65 dBc。
In order to counter active jamming, the radar system requires frequency synthesizer to have a frequency agility characteristics; and also requires the spurious suppression the higher the better, especially when the bandwidth of the output signal is wide. Limited by the size and cost, currently, the frequency agility frequency synthesizers are widely based on Direct Digital Synthesis（DDS） technology. Some research and analysis about frequency agility frequency synthesizer technology based on low spurious using DDS are involved in this thesis; simultaneously, a new DDS IC frequency agility frequency synthesizer with the DDS clock frequency up to 3.2 GHz is introduced. The bandwidth of the frequency agility frequency synthesizer is 250 MHz and its spurious suppression index is better than -65 dBc in the whole band.
出处
《信息与电子工程》
2011年第4期422-425,共4页
information and electronic engineering
关键词
频率捷变
DDS
杂散抑制
frequency agility
DDS
spurious suppression
