高速ADC中折叠电路的改进

The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design

针对8bit 125Ms/s折叠插值A/D转换器芯片设计,文中提出了一种新的折叠波产生算法,在低压设计中节省了电压设计余度.折叠电路的尾电流源采用低压宽摆幅的共源共栅结构,使差分对的尾电流源更匹配,改善了整个A/D转换器的非线性;折叠电路输出端采用跨阻放大器输出,提高了折叠电路输出端的带宽;采用共模反馈电路,使折叠输出的共模点更稳定,减小了折叠波的过零点失真.整个电路采用2.5V低电压设计,UMC 0.25μm的工艺模型参数,用Hspice对A/D电路进行模拟验证.结果表明,此电路取得了预期结果.

In the 8bit 125MHz Sample/s folding and interpolating A/D converter chip design,one new method of folding wave＇s production is put forward,which economize the voltage assignment in low-voltage analog design.The wide-swing Cascode topology is used in the tail currents design,which makes the tail currents of differential pairs match better,so DNL and INL of A/D convert system is reduced.A trans-resistance amplifier is used in the output nodes of folding circuit,which increase the analog bandwidth.The CMFB topology makes the common-mode level of output voltage more stable,which decreases zero-crossing distortion.In this project,VDD is 2.5V.The whole A/D system is simulated and validated in Hspice,and the simulation environment is 0.25μm CMOS process of UMC.