用LabVIEW FPGA模块实现不同时钟域的数据连续传输

LabVIEW FPGA-Based Data Continuous Transmission Between Two Clock Domains

为了解决基于LabVIEW FPGA模块的DMA FIFO深度设定不当带来的数据不连续问题,结合LabVIEW FPGA的编程特点和DMA FIFO的工作原理,提出了一种设定FIFO深度的方法。对FIFO不同深度的实验表明,采用该方法设定的FIFO深度能够比较好地满足系统对数据连续传输的要求。研究结果对深入展开研究和工程设计具有一定的指导意义。

In order to solve the problem of data transmission discontinuity caused by the improperly depth setting of DMA FIFO based on LabVIEW FPGA, a method of setting the depth of FIFO is presented in combination with the characteristic of LabVIEW FPGA and the working principle of DMA FIFO. The experiment of FIFO with different depth indicates that the method can satisfy the requirement of the continuity of data transmission. The result has a certain instruction meaning for further research and engineering design.