一种三维多层1TxR阻变存储器设计

A 3D Resistive Switch Memory with Stackable 1TxR Cell

提出一种适用于未来高密度应用的三维多层可堆叠1TxR阻变存储器设计.采用新型的多个存储电阻共享一个选通管的存储单元,选通管制作在硅片表面与标准逻辑工艺兼容,存储电阻堆叠在不同的互连金属层之间,构成三维存储结构.在0.13μm工艺下,以一个使用8层金属堆叠的1TxR(x=64)结构为例,其存储密度比传统的单层1T1R结构高280%.同时提出相关的读写操作方法来防止由漏电流造成的误写和误读并且降低功耗.

A novel 3D Resistive Switch Memory concept adopting stackable multi-layer 1TxR memory cell structure for future high density application is proposed.The access transistor fabricated on the top of silicon wafer is shared by several resistors.Resistors are stacked between different metallic layers to form 3D structure.For an 8-layer stacked metallic 1TxR（x=64） as an example,the density is over 280% higher than that of the conventional single layer 1T1R structure.Corresponding operation algorithm is proposed to inhibit effectively mis-write and mis-read caused by leakage current and reduce power consumption.