抗软错误SRAM单元设计

SRAM Cell Design to Improve Soft Error Tolerance

随着半导体工艺技术的发展,节点电容和电源电压的减小加剧了软错误对集成电路设计的影响.高能带电粒子入射SRAM单元敏感节点引起的软错误可能通过改变基于SRAM的FPGA的存储单元配置而改变芯片功能.在此类型FPGA芯片内,SRAM单元存放着FPGA的配置数据,因此增强SRAM的抗软错误性能是提升FPGA芯片可靠性的最有效方式之一.提出了一种具有良好抗软错误性能的SRAM单元结构8T-SRAM,并采用工业级65 nm CMOS工艺库对6T-SRAM,ASRAM0以及8T-SRAM单元的读/写速度、漏电功耗以及抗软错误性能进行了Spice仿真验证.仿真结果表明8T-SRAM结构抗软错误性能比传统的6T-SRAM以及ASRAM0更好,其软错误率比6T-SRAM结构减少了44.20%.

With the continuous technology scaling,the reduction of nodal capacitances and supply voltage have impacted severely the soft error rate of integrated circuits.Impacts of charged particle on the sensitive nodes could result in soft errors to modify the circuit functionality due to changing the configuration bits of SRAM based FPGA.Improving the soft error tolerance of SRAM would be one of the most efficient methods to enhance the reliability of the SRAM based FPGA,since the configuration data are stored in SRAM cells.One SRAM cell design,8T-SRAM,is proposed,which mainly aims at reducing the soft error rate in FPGA.The read/write speed,leakage power and the soft error tolerance of 6T-SRAM,ASRAM0 and 8T-SRAM are verified by using Spice simulation with the industrial 65nm CMOS techn-ology.Simulation result shows that the proposed SRAM design has better soft error immunity.The Soft Error Rate of 8T-SRAM is 44.20% less than that of the conventional 6T-SRAM.