应用于FPGA芯片时钟管理的锁相环设计实现

Design of PLL for Clock Management in FPGA

设计了一种嵌入于FPGA芯片的锁相环,实现了四相位时钟、倍频、半整数可编程分频、可调节相位输出功能,满足对于FPGA芯片时钟管理的要求.锁相环采用了自偏置结构,拓展了锁相环的工作范围,缩短了锁定时间,其阻尼系数以及环路带宽和工作频率的比值都仅由电容的比值决定,有效地减小了工艺、电压、温度等对电路的影响.锁相环采用0.18μm CMOS数字工艺,嵌入复旦大学自主研发的FPGA芯片FDP-Ⅱ,经过流片验证,实现了工作频率范围10~600 MHz,整体电路功耗仅为29 mW,锁定时间小于4μs,峰峰值抖动小于±145 ps.

A phase-locked loop（PLL） designed for FPGA based on self-biased technique is implemented in 0.18μm CMOS process.In the technique,the damping factor and the ratio of bandwidth to operating frequency are determined only by the capacity ratio,independent of process,voltage and temperature,thus extend the operating range and minimize the locking time.The PLL provides four-phase clock,programmable frequency synthesis and programmable phase-shift for clock management in FPGA.The PLL is embedded in FDP-Ⅱ,the test results show that the operating frequency of the PLL ranges from 10 to 600MHz and overall power consumption is only 29mW,the settle time is less than 4μs and the peak-to-peak clock jitter is less than±145 ps.