摘要
本文根据通信信号调制识别过程中瞬时相位去线性的原理,提出了便于硬件实现的最小均方算法,实现了对瞬时相位解混叠后的线性相位分量的滤除。改进后的算法在不增加硬件资源的情况下提高了运算精度。硬件电路的设计基于Quartus Ⅱ平台,用Verilog HDL语言编程实现。算法首先经过Matlab仿真,并在FPGA上通过测试,验证了其正确性和可行性。
In the processing of the automatic modulation recognition,the linear component of instantaneous phase needs to be removed.This article presents a method of minimum mean square which is easy to be implemented by hardware.The method can eliminate the instantaneous phase's linear component.The modified algorithm improves the computing accuracy without additional hardware resources.The design based on Quartus II platform is realized by using Verilog HDL language.By simulation with Matlab and test with FPGA,the validity and feasibility of the method are verified.
出处
《电路与系统学报》
CSCD
北大核心
2011年第4期116-119,共4页
Journal of Circuits and Systems
基金
国家自然科学基金--中物院联合基金资助项目(10876029)
关键词
瞬时相位
去线性
最小均方
硬件实现
instantaneous phase
removal of linear
minimum mean square
hardware realization