摘要
本文将脉冲功率领域中基于脉冲成型线的窄脉冲产生技术运用于芯片电路设计中,基于0.13μm的CMOS工艺,进行片上电路设计与实现。用CadenceTM Spectre Simulation进行了原理图和版图仿真分析,选用标准的片上共面波导(CPW)作为脉冲成型线(PFL),采用NMOS晶体管作为开关,仿真结果表明在共面波导的长度为268μm时,产生的窄脉冲宽度最小可达8ps。将共面波导长度为4mm的脉冲成型电路进行商业化0.13μm CMOS技术流片,在50Ω负载上测得的脉冲宽度约为160ps,幅值为110~180mV。
A traditional short pulse generator based on pulse forming circuit is implemented in a commercial 0.13 μm CMOS technology.This circuit is analyzed through CadenceTM Spectre simulation in which a standard on-chip meandered coplanar waveguide(CPW) is used as the pulse forming line and a CMOS transistor is used as the switch.An output pulse with the width of 8ps can be obtained when the length of CPW is 268μm.The proposed circuit with 4mm length CPW is fabricated and the pulses of ~160ps durations and 110-180 mV amplitudes on a 50Ω load are obtained when the power supply is tuned from 1.2 V to 2.0V.
出处
《电路与系统学报》
CSCD
北大核心
2011年第4期131-134,共4页
Journal of Circuits and Systems