摘要
在COTS微处理器上实现面向硬件故障的软件容错技术,与硬件容错技术相比,其性能、成本、功耗和灵活性上都拥有巨大的优势。其中容错编译技术通过在编译的时候自动地插入指令实现容错,实现简单、高效,不需要重写源代码,减轻了程序员的负担,有利于利用已有的大量程序,是软件容错研究中较为活跃的分支。本文以GNU开源编译器GCC为平台,结合现有容错编译算法,讨论一款初步具有容错编译能力的编译器的设计与实现。
Compared to the performance,cost,power and flexibility with the hardware fault-tolerant technique,the Software Implemented Hardware Fault Tolerance for COTS microprocessors hava many advantages.The fault tolerant compilation technology,which compiles at the compile time by automatically inserting instructions to achieve fault tolerance,which is easy-to-implement,efficient and does not need to rewrite the source code.And it reduces the burden for the programmer,and makes the existing programs easy-to-use.Currently,it is the more active branches in the software fault tolerance research.This paper takes the GNU compiler GCC as a platform,gives an approach of the design and implementation for a fault-tolerant compiler which combines with the existing fault-tolerant algorithms.
出处
《计算机工程与科学》
CSCD
北大核心
2011年第8期89-94,共6页
Computer Engineering & Science
关键词
容错编译
GCC
冗余计算
软件容错
fault tolerant compilation
GCC
redundance computing
software fault tolerance
