期刊文献+

光转换单元中锁相环带宽的优化

Optimization of bandwidth for phase-locked loop in OTU
下载PDF
导出
摘要 考虑光转换单元(OTU)中锁相环带宽同时受外部输入抖动和内部相位噪声抖动的影响,为克服锁相环带宽选择的矛盾性,本文对其带宽进行了优化设计。在同时考虑外部输入抖动和内部相位噪声的情况下,对锁相环带宽算法进行综合分析。通过改进前人的计算和分析方法推导得出OTU中锁相环带宽的优化算法,分析并得到锁相环路的优化带宽,使OTU的时钟输出有较低的抖动噪声。将优化算法应用到2.5 Gbit/s和10 Gbit/s的OTU中,对环路参数进行定量和定性分析,获得了锁相环的优化参数和再生器输出抖动值。实验研究表明,该优化算法具有一定优越性与可行性,比较适用于OTU。 As both the external input jitter and the internal phase noise jitter impact on the bandwidth of Phase-Locked Loop(PLL) in an Optical Transponder Unit(OTU),the bandwidth of the PLL was designed optimally to solve the contradiction of the wavelength selection.With consideration of the external input jitter and the internal phase noise,the bandwidth algorithm of the PLL was comprehensively analyzed,and an optimization algorithm of the bandwidth for PLL in the OTU was deduced through improving calculation and analytical methods from formers.The optimal bandwidth of the PLL can ensure the lower jitter noise of clock output in the OUT.The optimization algorithm was applied in the OTUs with 2.5 Gbit/s and 10 Gbit/s,respectively to analyze the loop parameters and the optimal parameters of the PLL and the output jitter value of a regenerator were acquired quantitatively and qualitatively.The experiment shows that the optimization algorithm is superior to traditional algorithms and more suitable for OTUs.
出处 《光学精密工程》 EI CAS CSCD 北大核心 2011年第8期1937-1943,共7页 Optics and Precision Engineering
基金 国家自然科学基金资助项目(No.61071117No.61003256) 重庆市自然科学基金资助项目(No.2010BB2409) 重庆市教委科学技术研究项目(No.KJ110519)
关键词 锁相环 优化算法 噪声 带宽 抖动 Phase-locked loop(PLL) optimization algorithm noise bandwidth jitter
  • 相关文献

参考文献10

  • 1GURUMOORTHY V,PALERMO S. Supply regu-lation techniques for phase-locked loops [C]. Cir- cuits and Systems Workshop ( DCAS 2009), Dallas IEEE, 2009 : 1- 4.
  • 2van der TANG J D, VAUCHER C S. Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters [C]. Electronics, Circuits and Systems (ICECS 2001), Poland Zako- pane, IEEE,2001:31-34.
  • 3张厥盛,郑继禹,万心平.锁相环技术[M].西安:西安电子科技大学出版社,2003.
  • 4KYOOHYUN L, PARK CH H, KIM D,et al.. A low-noise phase-locked loop design by loop band- width optimization [J]. IEEE Journal of Solid- State Circuits, 2000,35 ( 6 ) : 807- 815.
  • 5KROUPA V F. Phase Lock Loops and Frequency Synthesis[M]. West Sussex England: John Wiley Sons Ltd, 2003.
  • 6XIANG G, KLUMPERINK E A M, GERAEDTS P F J, et al.. Jitter analysis and a benehmarking figure-of-merit for phase-locked loops [J]. IEEE Transactions on Circuits and Systems Ⅱ : Express Briefs, 2009,56(2) : 117-121.
  • 7KHO J, LOH C I, WUI H M, et al.. Extended a- nalysis of SSN effect on phase-locked loop (PLL) circuit [C]. Electrical Design of Advanced Packa- ging &Systems Symposium(EDAPS 2009). Hong Kong, IEEE, 2009: 1- 4.
  • 8PEDRO R, JOSEP P, JOAN B, et al.. Decoupled double synchronous reference frame PLL for power converters control[J]. IEEE Trans. on Power E- lectronics, 2007,22(2) : 584-592.
  • 9KAMATH A S, CHATTOPADHYAY B A. 13 MHz input, 480 MHz output Fractional Phase Lock Loop with 1 MHz bandwidth[C]. Circuits and Systems (ISCAS 2010), Paris IEEE,2010: 501-504.
  • 10ARAKALI A,GONDI S, HANUMOLU P K. A- nalysis and design techniques for supply-noise mit- igation in phase-locked loops[J]. IEEE Journal of Circuits and Systems Ⅰ, 2010, 57 (11) : 2880- 2889.

共引文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部