摘要
基于0.18μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC。芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准。测试结果表明,ADC在1.4 GHz采样率下,有效位达6.4bit,功耗小于480 mW。文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出其在超高速ADC中的必要性。
A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS.The chip realizes cascade folding and interpolation with resistive averaging and digital calibration.Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s.The proposed effective calibration methods could improve the static and dynamic performance of ADC.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2011年第4期393-397,共5页
Research & Progress of SSE
关键词
模数转换器(ADC)
失调校准
折叠内插
analog-to-digital conversion
offset calibration
folding and interpolation
