2．06GHz～3．43GHz自校准频率综合器设计

Design of a 2.06 GHz～3.43 GHz Frequency Synthesizer with Auto-Calibration Loop

提出了一种自校准频率综合器,通过采用开关电容阵列使该设计具有较低的相位噪声和较宽的调谐范围。自校准控制回路的引入,使该综合器能根据输入参考频率,温度,分频比等参数自动调整开关阵列中开关的开启和关断,达到快速锁定的目的。采用SMIC 0.18μm CMOS工艺进行仿真,结果显示,频率综合器输出频率范围从2.06GHz至3.43GHz(50%),最差相位噪声为-127.9dBc/Hz@1MHz,在1.8V电源电压下,频率综合器的功耗约为12mW。

A kind of auto-calibration frequency synthesizer was proposed. By using the switch electric capacity array,this design can be made it work in a low phase noise and a wide tuning range. The adaptive control return route enables this synthesizer to act, according to the parameters such as the input reference frequency, the input temperature and the rate of requency derision, on turning off or turning on switches in the automatic control switch array,and achieves fastly the fixed aiming goal. The SMIC 0. 18μm CMOS craft is provided to carry on the simulation. Finally the frequency synthesizer demonstrates its output frequency range from 2.06 GHz to 3.43 GHz （50%） ,the worst phase noise -127.9 dBc/Hz at 1 MHz,its power loss about 12 mW under the supply voltage 1. SV.