基于随机访问扫描的低功耗确定性测试方案

A low power deterministic test scheme based on random access scan structure

大规模高密度的集成电路在测试中面临着测试数据量大、测试时间长和测试功耗高的问题.为此提出了一种基于随机访问扫描(random access scan,RAS)的混合模式测试体系结构,该测试方法先通过自动测试模式生成一个确定测试集,再将确定测试集嵌入片上生成的测试序列中进行确定性测试.测试分两个阶段进行,第一阶段利用块固定折叠计数器生成的具有块固定特征的测试模式序列,测试电路中的大部分故障;第二阶段,通过位跳变方法生成确定测试模式,测试剩余的难测故障.在ISCAS-89基准电路上的实验结果表明,该方案不仅减少了测试存储量和测试时间,而且有效地降低了测试功耗.

High density and large scale IC faces many problems during tests,such as huge amounts of test data,long test application time and high test power dissipation.A test scheme based on random access scan architecture for mixed-mode test was proposed.A pre-computed set of deterministic test cubes were embedded in test sequences generated on chip.The test process consists of two steps.The first step relied on a new type of test pattern generator called block-fixing folding（BFF） counter.The deterministic test cubes that detect most of the faults in the circuit under test were embedded into BFF test sequences.In BFF sequences,many blocks were fixed for increasing the efficiency of generating test patterns.The second step was to generate the remainder deterministic test patterns for hard-to-test faults by the bit-flipping approach.Experimental results on ISCAS-89 benchmark show that this scheme can not only reduce test data volume and test application time effectively,but also reduce test power consumption significantly.