摘要
设计了一个基于TSMC0.18μmCMOS工艺的2.0 GHz全差分CMOS低噪声放大器。根据电路结构特点,对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;采用在输入级增加电容和选择小值LC并联网作为差分电路的负载的方法,在改善输入匹配网络特性的同时,提高了电路的增益。仿真结果表明该放大器较好地满足了小信号放大器的指标要求,可以用于射频输入电路的前端。
This article designed a 2.0 GHz difference CMOS low noise amplifier based on TSM C 0.18 μm CMOS technology.Aecording to the characteristics of the circuit stru cture,LNA was noise-optimized under the restriction on power to select optimal transistor gate.By increasing capacitance in input and selecting small value L C networking as the load of differential circuit,the characteristics of input i mpedance matching networks were improved,and the circuit gain was enhanced as w ell.The simulation results show that the amplifier well meets the index require ments of small signal amplifier and can be used for RF input login front-end.
出处
《实验室研究与探索》
CAS
北大核心
2011年第8期232-235,共4页
Research and Exploration In Laboratory
关键词
差分结构
低噪声放大器
噪声系数
输入匹配
CMOS工艺
difference structure
low noise amplifier（LNA）
noise factor
input impedance m atching
CMOS technology
