一种有效的内环AGC电路

Effective Inner Loop AGC Circuit

设计了一款应用于移动数字电视调谐器芯片中的数字式内环自动增益控制(Automatic Gain Control,AGC)电路。该控制电路采用的算法有效避免了死循环的问题,并且提高了AGC电路的响应时间。电路设计利用Verilog硬件描述语言进行描述,通过了功能仿真并在FPGA上进行了验证。最终采用TSMC 0.13μm CMOS工艺,完成了电路版图。芯片面积在126μm×106μm,平均功耗在3.876 mW左右。

In this paper, a digital-controlled inner loop Automatic Gain Control （AGC） circuit used in a mobile digital TV tuner chip is proposed. The algorithm of the control circuit can avoid the infinite loop problem, and improve the response time of AGC circuit. The circuit is described in hardware language of Verilog, and has been simulated and verified on the FPGA development board. The whole circuit is manufactured in TSMC 0.13 IJnn CMOS process. The core area of the layout is about 126 μmX.m, the average power consumption is about 3.876 mW with a supply vokage of 1.2 V.