基于FPGA的3DES加密系统的设计与实现

Implementation and Design of 3DES Based on FPGA

针对网络通信安全问题,分析了3DES加密算法的原理,描述了该算法FPGA设计的高速实现,各个模块均用硬件描述语言(VHDL)实现。系统最终在Xilinx ISE 10.1开发工具下进行编译、仿真验证及逻辑综合,完成了对数据的加解密运算。仿真结果表明,该系统可广泛应用于网络安全产品及其电子安全设备中。

In view of the network communication security problems, the principle of 3DES encryption algorithm is ana- lyzed, and the high-speed FPGA implementation of the algorithm is described. In this system, each module can be realized by using hardware description language（VHDL）. The compilation, simulated verification and logic synthesis are performed by the development tool of Xilinx ISE 10.1 to complete encrypting-deciphering of the data. The result indicates that the design can be used in network security products and other electronic security equipment extensively.