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可去抖动的时钟脉冲发生器 被引量:3

Design of jitter-removable clock pulse generator
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摘要 为了克服晶体振荡器的温漂问题,提高时钟精度,控制输出脉冲。本文设计了一种脉冲发生器,采用基于分频链的时钟校准方法,结合脉冲控制电路,可以输出标准时钟脉冲。标准时钟脉冲在脉冲发生器的控制下产生频率和脉冲个数都可调节的脉冲序列,其校准精度达±0.25 ppm,校准范围±32 ppm。经仿真验证,该方案符合设计初衷,达到设计要求。 In order to overcome the temperature drift of the crystal oscillator, improve the clock precision and control the pulse output, a calibration algorithm based on divide-chain frequency is proposed, thus, a pulse generator can be adjusted to produce standard clock pulses, whose frequency and number can be controlled with the help of a pulse control circuit. Simulation results show that, the calibration accuracy is ±0. 25 ppm, and the range of calibration is ±32 ppm. That is, the solution meets the design requirements well.
出处 《西安邮电学院学报》 2011年第5期72-75,共4页 Journal of Xi'an Institute of Posts and Telecommunications
关键词 Verilog-HDL晶体振荡器 校准 脉冲控制 Verilog-HDL crystal oscillator calibration pulse control
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共引文献123

同被引文献15

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