摘要
为了解决上电复位电路的可靠性和功耗之间的矛盾,给出了一种新型低功耗上电复位电路的设计方法。该方法基于0.5μmCMOS工艺模型,并采用Hspice仿真工具进行模拟仿真。结果显示:其典型条件下的电源电流消耗仅为2.8μA;在电源慢速上电情况下,上拉电压典型值为0.682V,下拉电压典型值为2.057V;在电源电压瞬间上电(10ns内)情况下,其复位脉宽典型值为0.95μs;而通过对电源电压进行正向和反向DC扫描,所得到的滞回电压典型值为150mV。该电路可以成功应用于电源IC的设计中。
A new power-on reset circuit with low power consumption is designed in order to address the disparity between reliability and power consumption. This circuit is simulated with a 0.5 vm CMOS process model by HSPICE. Results show that the supply current consumption is only 2.8μA under typical conditions. With power supply voltage at slow power-on, the pull-up voltage is typically 0. 682 V and the pull-down voltage is typically 2. 057 V. With power supply voltage in step response, the reset pulse width is typically 0.95μs. The hysteresis voltage is typically 150mV by the forward and reverse scanning of power supply voltage. The circuit has been successfully applied to the power management of IC design.
出处
《物联网技术》
2011年第7期52-54,57,共4页
Internet of things technologies
关键词
上电复位
低功耗
下拉电压
滞回电压
power-on reset
low dissipation
pull-down voltage
hysteresis voltage
