加法器溢出处理的优化设计与实现

The Optimization Design and Implementation Method for an Adder with Overflow Processing

本文提出了一种带溢出处理功能的加法与分支模块的新结构。这种结构无需等待特定的溢出判断信号,从而减少了溢出处理的延时开销。本文主要针对关键路径上控制信号的竞争问题,提出了两种解决方案。基于数学的角度重新分析各控制信号与数据输入之间的关系,把较早到达的0或1提前参与运算。而把较晚到达的0或1推迟参与运算,利用前一级运算的时间生成晚到的控制信号,成功地解决了关键路径上控制信号的竞争问题。此设计在0.13μmCMOS工艺中实现,版图后仿真最大延时为590ps,较之前结构减少了210ps,达到预期优化目的,实现了时序收敛,有效地提高了加法器的运算效率。

This paper introduces a new structure for adders and branch modules with overflow processing. The particular overflow judgement signals are needless,so it reduces the time overhead of the overflow processing. For the problem of control signals race on critical paths, two resolutions are given. Based on the view of mathematics, we re-analyse the relationship between control signals and input data, calculate the earlier arrived 0/1 signals firstly, and deferre the calculation time of the later arrived 0/1 signals. We make use of the previous stage＇s operating period to raise the later arrived control signals, and so we succeede in the contention problem between the control signals. Finally we implement the de- sign with the 0.13μm CMOS technology,and the maximum delay of the post-layout simulation is 590ps with 210ps off compared with the previous designs. It achieves the desired optimal purpose, and meets calculation efficiency.