基于Avalon总线的计数器接口IP核设计及应用

Design and Application of Counter's Interface IP Core Based on Avalon Bus

在控制领域,随着基于FPGA的NIOS II软核处理器的广泛应用,NIOS II的Avalon总线与外设的接口IP(知识产权)核的研究就显得很有价值。该设计结合FPGA实现了编码器脉冲的整形、滤波、倍频、鉴相、计数和锁存功能,然后运用Verilog语言完成了计数模块与Avalon总线的接口IP核设计,最后采取SOPC(可编程片上系统)技术定制了NIOS II软核处理器。实际运用表明,该设计稳定可靠,能有效准确地获取脉冲,简化了电路。

With the wider application of the NIOS II soft processor based on FPGA in the control field,the research of the interface IP （intellectual property） core between NIOS II＇s Avalon bus and peripheral appears very valuable.This design realizes the function of encoder pulses＂ shaping,filtering,frequency multiplication,checking phase,counting and latching,which combines FPGA,then making use of verilog language to finish the design of counting model and Avalon bus＇s interface IP core,finally adopting SOPC（program system on chip） technology to order a NIOS II soft processor.