基于FPGA的高性能计算中全局流水的研究

Research of pipeline with FPGA in HPC

针对FPGA的全局流水进行了研究,采用CPU+FPGA的混合架构,论证了FPGA实现全局流水的优越性:使用FPGA进行全局流水可以在CPU处理过程中减少FPGA等待时间,提高FPGA的利用率;可以减少FPGA与CPU之间的通信量以及程序在CPU端的存储开销;可以均衡CPU负载,使得CPU有空闲时间处理其它任务。用N-Body的FMM算法作为例子,对优越性分别作了分析,并设计了实验方案,实验结果表明了FPGA实现全局流水的优越性。

The pipeline with FPGA is studied, the advantage of the pipeline with FPGA： reduction on the spare time of FPGA whenCPU processing, decreasing amounts of communication between FPGA and CPU, balancing the load of CPU in order to save the power ofCPU. An experiment scheme with FMM algorithm is designed and run on CPU＋FPGA heterogeneous architecture. Finally, the result of experiments prove the advantage of pipeline with FPGA.