一种面向多核处理器的通用可调试性架构

A General DFD Infrastructure for Chip Multiprocessor

硅后调试对于当代集成电路设计变得日益重要,用于辅助硅后调试的可调式性设计(DFD)应运而生.由于多核处理器往往包含多种不同类型的部件,每个部件都有各自的调试功能需求,极大地提高了可调式性设计的复杂度.针对上述问题,提出一种面向片上多核处理器的通用可调试性架构.该架构使用简单的监测器来监测和控制处理器中用于互连的片上网络,通过专门的调试总线将各个监测器与调试总控模块连接在一起,并使用EJTAG通用调试接口与外部调试主机传递信息.与传统的可调试性架构相比,该架构无需片上RAM,硬件代价低,具有模块化的特性.此外,文中提出的架构采用了工业界通用的EJTAG调试接口,因此通用性较高,已经被应用于龙芯-3B多核处理器中.实验结果显示,该架构可以在高频高数据带宽的环境下工作.

Post-silicon debugging is becoming more and more important in modern integrated circuit design. Hence, design for debug （DFD） is proposed to facilitate post-silicon debugging. The DFD in multi-core processors are very complicate, as there are lots of different components contained in a multi-core processor, and each of them have its own debugging requirements. In this paper, we propose a general DFD infrastructure for chip multiprocessor （CMP） that contains several simple monitors to watch and control the network on chip （NoC）. All monitors are connected to a centralized controller, which gathers information and communicates with debugging host using EJTAG port. Compared with traditional DFD infrastructures, the proposed infrastructure is modularized, low cost, and general. This DFD infrastructure has been adopted by a state-of-art industry CMP Godson-3B. Experimental results demonstrated that the DFD infrastructure can work under high frequency and high data bandwidth environments.