基于FPGA的双通道语音增强系统设计与实现

Design and Implementation of Dual Channel Speech Enhancement System Based on FPGA

在数字助听器和小型语音设备的实际应用中,非平稳噪声干扰与自适应方法的收敛过程会造成语音性能下降。为了实际解决该问题,设计了一种新型的实时语音增强系统。该系统基于双通道一阶差分麦克风阵列,同时采用结构分时复用和高效汉宁窗分帧等方法,提高了性能并节约了硬件成本。该语音增强系统可获得3.5db左右的信噪比增益,同时克服了单通道增强系统和自适应方法的局限,并用Verilog语言在FPGA上设计实现该系统。从而在硬件层次上提高了小型语音设备的抗噪性能,为数字助听器或相关ASIC芯片的研制奠定了基础。

In the processing of practically using Digital Hearing Aids and miniaturized speech devices,non-stationary noises and the processing of adaptive convergence will impair speech performance.To deal with these problems,this paper has designed a new real-time Speech Enhancement System.The system uses dual channel first-order differential microphone array,and makes use of time division multiplexing and efficient Hanning windows,so this system can obtain high performance and save hardware cost.The system is able to achieve a 3.5 dB signal-to-noise ratio gain,and has been implemented by Verilog on FPGA,avoiding some problems and limits of single channel or adaptive method speech Enhancement system.So,improving anti-noise performance of miniaturized speech devices on the level of hardware,this design lays a foundation for RD of Digital Hearing Aids and involved ASIC.