基于高速串行ADC的并行采集模块设计

Design of parallel acquisition module based on the high-speed serial ADC

串行总线技术可以获得更高的性能,具有更高的传输速率和更低的设计成本,被广泛应用于高速通信领域。基于高速串行LVDS输出的ADC利用时间交替并行采样技术设计实现了1个并行采集模块,主要阐述了采样时钟的相移设计与2 GSPS采样率的实现、串行数据的传输与处理、DDR模式下1∶8串并转换器在FPGA平台中的设计与实现,并介绍了高速串行ADC芯片的工作模式。结果表明,采用Xilinx Spartan-6系列的ISERDES2模块设计的串并转换器最终达到了16 Gbit/s的串行数据吞吐量,满足了设计要求。

Serial bus technology can achieve higher performance,higher transmission rate and lower design costs,is widely applied in high-speed communications.The study,based on high-speed serial LVDS outputs of the ADC,using time alternating parallel sampling technique designed and implemented a parallel acquisition module,mainly on the design of phase shift about the sampling clock and implementation of 2 GSPS sampling rate,the transmission and processing of the serial data,the realization of 1∶8 DDR serial-to-parallel converter based on FPGA platform,and introduced the working mode of high-speed serial ADC chips.The results show that the design of serial-to-parallel converter in the use of ISERDES2 module in Xilinx Spartan-6 series,finally reached 16 Gbit/ s serial data rate to meet the design requirements.